• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The XIO2001 is a single-function PCI Express to PCI translation bridge that is fully compliant to the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. For downstream traffic, the bridge simultaneously supports up to eight posted and four non-posted transactions. For upstream traffic, up to six posted and and four non-posted transactions are simultaneously supported.

The PCI Express interface is fully compliant to the PCI Express Base Specification, Revision 2.0.

The PCI Express interface supports a ×1 link operating at full 250 MB/s packet throughput in each direction simultaneously. Also, the bridge supports the advanced error reporting including extended CRC (ECRC) as defined in the PCI Express Base Specification.

特性

• Full ×1 PCI Express Throughput
• Fully Compliant with PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0
• Fully Compliant with PCI Express Base Specification, Revision 2.0
• Fully Compliant with PCI Local Bus Specification, Revision 2.3
• PCI Express Advanced Error Reporting Capability Including ECRC Support
• Support for D1, D2, D3_hot, and D3_cold
• Active-State Link Power Management Saves Power When Packet Activity on the
  PCI Express Link is Idle, Using Both L0s and L1 States
• Wake Event and Beacon Support
• Error Forwarding Including PCI Express Data Poisoning and PCI Bus Parity Errors
• Utilizes 100-MHz Differential PCI Express Common Reference Clock or 125-MHz
  Single-Ended, Reference Clock
• Optional Spread Spectrum Reference Clock is Supported
• Robust Pipeline Architecture To Minimize Transaction Latency
• Full PCI Local Bus 66-MHz/32-Bit Throughput
• Support for Six Subordinate PCI Bus Masters with Internal Configurable,
  2-Level Prioritization Scheme
• Two Package Options: 12 mm × 12 mm and 7 mm × 7 mm
• Internal PCI Arbiter Supporting Up to 6 External PCI Masters
• Advanced PCI Express Message Signaled Interrupt Generation for Serial IRQ Interrupts
• External PCI Bus Arbiter Option
• PCI Bus LOCK Support
• JTAG/BS for Production Test