说明

The XIO1100 is a PCI Express™ PHY that is compliant with PCI Express Base Specification Revision 1.1 and that interfaces the PCI Express Media Access Layer (MAC) to a PCI Express serial link by using a modified version of the interface described in PHY Interface for the PCI Express™ Architecture (also known as PIPE interface) by Intel Corporation. This modified version of the PIPE interface is referred to as a TI-PIPE interface throughout this data manual.

The TI-PIPE interface is a pin-configurable interface that can be configured as either a 16-bit or an 8-bit interface.

• The 16-bit TI-PIPE interface is a 125 MHz 16-bit parallel interface with a 16-bit output bus (RXDATA) that is clocked by the RXCLK output clock and a 16-bit input bus (TXDATA) that is clocked by the TXCLK input clock.

特性

• X1 PCI Express™ Serial Link
  • PCI Express 1.1 Compliant
  • Selectable Reference Clock (100 MHz, 125 MHz)
  • Low-Power Capability
• TI-PIPE MAC Interface
  • Source-Synchronous TX and RX Ports
  • 125 MHz TX/RX Clocks
  • Selectable 16-Bit SDR or 8-Bit DDR Mode
• 100-Pin MicroStar™ BGA Package
• Selectable 1.5-V or 1.8-V LVCMOS Buffers.

TI and MicroStar BGA are trademarks of Texas Instruments Incorporated
PCI Express is a trademark of PCI-SIG