• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The TL16C554 and the TL16C554I are enhanced quadruple versions of the TL16C550B asynchronous communications element (ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the quadruple ACE can be read at any time during functional operation by the CPU. The information obtained includes the type and condition of the operation performed and any error conditions encountered.

The TL16C554 and the TL16C554I quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes.

特性

• Integrated Asynchronous Communications Element
• Consists of Four Improved TL16C550 ACEs Plus Steering Logic
• In FIFO Mode, Each ACE Transmitter and Receiver Is Buffered With 16-Byte FIFO to Reduce the Number of Interrupts to CPU
• In TL16C450 Mode, Hold and Shift Registers Eliminate Need for Precise Synchronization Between the CPU and Serial Data
• Up to 16-MHz Clock Rate for up to 1-Mbaud Operation
• Programmable Baud Rate Generators Which Allow Division of Any Input Reference Clock by 1 to (2¹⁶-1) and Generate an Internal 16 × Clock
• Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and Parity) to or From the Serial Data Stream
• Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts
• Fully Programmable Serial Interface Characteristics:
  • 5-, 6-, 7-, or 8-Bit Characters
  • Even-, Odd-, or No-Parity Bit
  • 1-, 1 1/2-, or 2-Stop Bit Generation
  • Baud Generation (DC to 1-Mbit Per Second)
• False Start Bit Detection
• Complete Status Reporting Capabilities
• Line Break Generation and Detection
• Internal Diagnostic Capabilities:
  • Loopback Controls for Communications Link Fault Isolation
  • Break, Parity, Overrun, Framing Error Simulation
• Fully Prioritized Interrupt System Controls