• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The TL16C550C and the TL16C550CI are functional upgrades of the TL16C550B asynchronous communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the TL16C550C and the TL16C550CI, like the TL16C550B, can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow using RTS\ output and CTS\ input signals.

特性

• Programmable Auto-RTS\ and Auto-CTS\
• In Auto-CTS\ Mode, CTS\ Controls Transmitter
• In Auto-RTS\ Mode, RCV FIFO Contents and Threshold Control RTS\
• Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Power Drop
• Capable of Running With All Existing TL16C450 Software
• After Reset, All Registers Are Identical to the TL16C450 Register Set
• Up to 16-MHz Clock Rate for up to 1-Mbaud Operation
• In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data
• Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (2¹⁶ –1) and Generates an Internal 16× Clock
• Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream
• 5-V and 3.3-V Operation
• Independent Receiver Clock Input
• Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled
• Fully Programmable Serial Interface Characteristics:
  • 5-, 6-, 7-, or 8-Bit Characters
  • Even-, Odd-, or No-Parity Bit Generation and Detection
  • 1-, 1 1/2-, or 2-Stop Bit Generation
  • Baud Generation (dc to 1 Mbit/s)
• False-Start Bit Detection
• Complete Status Reporting Capabilities