• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The SLK2721 device is a single chip, multirate transceiver that derives high-speed timing signals for SONET/ SDH-based equipment. The device performs clock and data recovery, serial-to-parallel/parallel-to-serial conversion, and a frame detection function conforming to the SONET/SDH standards.

The device can be configured to operate under OC-48, OC-24, OC-12, or OC-3 data rate through the rate selection pins or the autorate detection function. An external reference clock operating at 622.08 MHz is required for the recovery loop, and it also provides a stable clock source in the absence of serial data transitions.

The SLK2721 device accepts 4-bit LVDS parallel data/clock and generates a NRZ SONET/SDH-compliant signal at the OC-3, OC-12, OC-24, or OC-48 data rate.

特性

• Fully Integrated SONET/SDH Transceiver to Support Clock/Data Recovery and Multiplexer/Demultiplexer Functions
• Enhanced Jitter Tolerance Over SLK2701
• Supports 2.7 Gbps OC-48 FEC Rate, OC-48, OC-24, OC-12, Gigabit Ethernet, and OC-3 Data Rate With Autorate Detection
• Supports Transmit Only, Receiver Only, Transceiver and Repeater Functions in a Single Chip Through Configuration Pins
• Supports SONET/SDH Frame Detection
• On-Chip PRBS Generation and Verification
• Supports 4-Bit LVDS (OIF99.102) Electrical Interface
• Single 2.5-V Power Supply
• Interfaces to Back Plane, Copper Cables, or Optical Modules
• Hot Plug Protection
• Low Jitter PECL-Compatible Differential Serial Interface With Programmable De-Emphasis for the Serial Output
• On-Chip Termination for LVDS and PECL-Compatible Interface
• Receiver Differential Input Thresholds 150 mV Minimum
• Supports SONET Loop Timing
• Low Power <900 mW at OC-48 Data Rate
• ESD Protection >2 kV
• 622-MHz Reference Clock
• Maintains Clock Output in Absence of Data
• Local and Remote Loopback
• Parity Checking and Generation for the LVDS Interface